verilog/sv questions

what is the output of the following code

clock is a peridoic square wave (clock signal) with a period of 10

always @(negedge clock)
if( posedge clock )
#5 out = ~clock;

2.

fork

T1:

T2:

T3: begin

E2 = E1;

while(1) -> E2;

end

join

when will the processes and finally for-join finish and in which order

what happens if E2 = E1 is placed before fork-join